Many kinds of electronic systems make use of magnetic devices including both digital systems, such as memories, and analog systems such as magnetic field sensors. Digital data memories are used extensively in digital systems of many kinds including computers and computer systems components, and digital signal processing systems. Such memories can be advantageously based on the storage of digital symbols as alternative states of magnetization in magnetic materials provided in each memory storage cell, the result being memories which use less electrical power and do not lose information upon removals of such electrical power.
Such memory cells, and magnetic field sensors also, can often be advantageously fabricated using ferromagnetic thin-film materials, and are often based on magnetoresistive sensing of magnetic states, or magnetic conditions, therein. Such devices may be provided at a surface of a monolithic integrated circuit to provide convenient electrical interconnections between the device and the operating circuitry therefor.
Ferromagnetic thin-film memory cells, for instance, can be made very small and packed very closely together to achieve a significant density of information storage, particularly when so provided on the surface of a monolithic integrated circuit. In this situation, the magnetic environment can become quite complex with fields in any one memory cell affecting the film portions in neighboring memory cells. Also, small ferromagnetic film portions in a memory cell can lead to substantial demagnetization fields which can cause instabilities in the magnetization state desired in such a cell.
These magnetic effects between neighbors in an array of closely packed ferromagnetic thin-film memory cells can be ameliorated to a considerable extent by providing a memory cell based on an intermediate separating material having two major surfaces on each of which an anisotropic ferromagnetic memory thin-film is provided. Such an arrangement provides significant “flux closure,” i.e. a more closely confined magnetic flux path, to thereby confine the magnetic field arising in the cell to affecting primarily just that cell. This result is considerably enhanced by choosing the separating material in the ferromagnetic thin-film memory cells to each be sufficiently thin. Similar “sandwich” structures are also used in magnetic sensors.
In the recent past, reducing the thicknesses of the ferromagnetic thin-films and the intermediate layers in extended “sandwich” structures, and adding possibly alternating ones of such films and layers, i.e. superlattices, have been shown to lead to a “giant magnetoresistive effect” being present in some circumstances. This effect yields a magnetoresistive response which can be in the range of up to an order of magnitude or more greater than that due to the well known anisotropic magnetoresistive response.
A memory cell based on the “giant magnetoresistive effect” can be provided by having one of the ferromagnetic layers in the “sandwich” construction being prevented from switching the magnetization direction therein from pointing along the easy axis therein in one to the opposite direction in the presence of suitable externally applied magnetic fields while permitting the remaining ferromagnetic layer to be free to do so in the same externally applied fields. In one such arrangement, a “spin-valve” structure is formed by providing an antiferromagnetic layer on the ferromagnetic layer that is to be prevented from switching in the externally applied fields to “pin” its magnetization direction in a selected direction. In an alternative arrangement often termed a “pseudo-spin valve” structure, the ferromagnetic layer that is to be prevented from switching in the externally applied fields is made sufficiently thicker than the free ferromagnetic layer so that it does not switch in those external fields provided to switch the free layer.
An alternative digital data bit storage and retrieval memory cell suited for fabrication with submicron dimensions can be fabricated that provides rapid retrievals of bit data stored therein and low power dissipation by substituting an electrical insulator for a conductor in the nonmagnetic layer. This memory cell can be fabricated using ferromagnetic thin-film materials of similar or different kinds in each of the magnetic memory films used in a “sandwich” structure on either side of an intermediate nonmagnetic layer which ferromagnetic films may be composite films, but this intermediate nonmagnetic layer conducts electrical current therethrough based primarily on a quantum electrodynamic effect “tunneling” current, or spin dependent tunneling.
Operating magnetic fields imposed externally are typically used to vary the angle of the magnetization vector with respect to the easy axis in the ferromagnetic films of these various kinds of magnetoresistive memory cell devices, particularly the free layers. Such operational magnetic fields imposed externally can be used to vary the angle to such an extent as to cause switching of the layer magnetization vector between two stable states which occur for the magnetization being oriented in opposite directions along the easy axis of the layer, the state of the cell determining the value of the binary bit being stored therein. One of the difficulties in such memories is the need to provide memory cells therein that have sufficiently uniform switching thresholds and adequate resistance to unavoidable interjected magnetic field disturbances in the typical memory cell state selection scheme used. This externally applied operating fields scheme is based on selective externally imposed magnetic fields provided by selectively directing electrical currents over or through sequences of such cells along corresponding electrical conductors so that selection of a cell occurs through providing coincident currents through two spatially crossing conductors (at a cross-point) to provide coincident presences of such fields at that cell. Such a coincident interjected magnetic fields memory cell state selection scheme is very desirable in that an individual switch, such as that provided by a transistor, is not needed for every memory cell, but the limitations this selection mode imposes on the uniformity of switching thresholds for each memory cell in a memory make the production of high yields difficult.
There is a further difficulty with such an externally applied coincident operating fields scheme memory in which a switch such as a transistor is not used with each cell. In those of such memories that have each spatially crossing pair of conductors electrically about but not connected to its corresponding cell at the cross-point, the unselected cells passed over by these conductors have half the magnetic field needed for switching the current magnetic state of the cell to another state. This increases the possibility of such cells being switched by the occurrence of random “noise” events with such a start toward switching being provided. Because of use of sensing currents that have a relatively small magnitude, this is not usually a problem during cell magnetic state determination processes.
In those of such memories that have each spatially crossing pair of conductors electrically connected to its corresponding cell, however, the resulting arrays of spatially crossing electrical conductors connected to the array of cells also leads to alternative electrical current paths occurring in those memories in addition to the desired current path through a selected one of those cells. The resulting voltage drops from these alternative path electrical currents that then occur over the various other cells of the array, in addition to the voltage drop across the selected cell, can result in making the determination of, or the setting of, a magnetic state in the selected cell either haphazardly correct or incorrect, or even impossible to determine. Thus, a cell switch being provided for each memory cell has often been required to make the operation thereof as a data memory acceptable, but the provision of such a switch for each cell adds to the area of each cell taken in the surface area of the integrated circuit chip in which the cell is provided which thereby reduces cell areal density and so increases memory chip cost.
There is another kind of magnetoresistive memory cell devices which can have the angle of the magnetization vector of the ferromagnetic films forming their the free layers varied with respect to the easy axis in those films without use of externally imposed operating magnetic fields. These devices are also multiple layer “sandwich” structure magnetoresistive memory cells but are switched between the magnetic states of such memory cells through selecting a particular cell and then controlling the supply of spin polarized electrical currents established therethrough, using switching transistors, to maintain or reverse the magnetization direction of a soft magnetic material layer in the cell device, and this is accomplished in the absence of any externally applied magnetic fields coincident therewith.
A spin polarized electrical current has therein electrons flowing with their spins aligned in one direction predominating the number of electrons therein with spins aligned in the opposite direction. Such spin injection currents with the spins of electrons therein predominating in one direction or the other lead to a corresponding spin injection torque on the device magnetic material free layer magnetization, if oriented in the opposing direction, that is sufficient to reverse the direction thereof as a device magnetic state change, and such currents can be reduced in magnitude if the device is such that they also cause substantial heating of the switched device. Such spin current switched magnetoresistive device memory cells thus avoid the need of providing adjacent thereto electrical current conductors with which to generate magnetic fields thereabout for operating those devices. The magnetic state of a device is determined by passing a much smaller sensing current through the device as the basis of determining its electrical resistance with one of two alternative resistance values indicating which one of the two corresponding alternative magnetic states the device is currently in.
Each of the spin current switched magnetoresistive devices in such memory cells has a vertical stacked structure supported on a silicon substrate, for example, as representatively shown in the cross section side view layer diagram in FIG. 1 of such cell devices, 10, though with many of the structural portions shown there having been reduced or exaggerated in that view for purposes of clarity. Devices 10, as supported, are otherwise surrounded by an electrical insulating material, typically silicon dioxide or silicon nitride, except for the row and column interconnection conductors connected thereto. FIG. 2 provides a perspective view of a portion of a monolithic integrated circuit of a cross-point magnetoresistive memory having therein an array of such spin current switched magnetoresistive device memory cell devices 10 with respect to which the foregoing cell selection, and the cell state setting and state determination processes are to be used.
A pair of 50 Å thick ferromagnetic layers, 11 and 12, have a 9 Å thick ruthenium layer, 13, provided therebetween to form data bit storage layers. On the other side of ferromagnetic layer 12 directly supporting that layer is a 4 Å thick layer of copper, 14, as an electron spin scattering layer, and directly on the other side of ferromagnetic layer 11 is a 4 Å thick aluminum oxide baffler layer, 15. Another 50 Å thick ferromagnetic layer, 16, directly supporting scattering layer 14 is a fixed magnetization direction layer as part of a synthetic antiferromagnet. A similar 50 Å thick ferromagnetic layer, 17, directly on barrier layer 15, completes a magnetic tunnel junction with barrier layer 15 between ferromagnetic layers 11 and 17, and also forms a fixed magnetization direction layer as part of a synthetic antiferromagnet.
A 9 Å thick ruthenium layer, 18, as an antiparallel coupling and electron spin scattering layer, is provided directly supporting ferromagnetic layer 16, and another 9 Å thick ruthenium layer, 19, again as an antiparallel coupling and electron spin scattering layer, is provided directly on ferromagnetic layer 17. A ferromagnetic layer, 20, as part of the synthetic antiferromagnet formed with layers 16 and 18 in being coupled by layer 18 antiparallel to layer 16, is provided directly supporting ruthenium layer 18, and a further ferromagnetic layer, 21, as part of the synthetic antiferromagnet formed with layers 17 and 19 in being coupled antiparallel by layer 19 to layer 17, is provided directly on ruthenium layer 19. A chrome platinum manganese antiferromagnetic layer, 22, directly supports ferromagnetic layer 20 to complete the formation of the pinned synthetic antiferromagnet to pin the magnetization direction of ferromagnetic layer 16 in a selected direction. Similarly, a chrome platinum antiferromagnetic layer, 23, is directly on ferromagnetic layer 21 to complete the formation of the pinned synthetic antiferromagnet to pin the magnetization direction of ferromagnetic layer 17 in the same direction as that of ferromagnetic layer 16 along the length of the cell.
A tungsten plug, 24, extending through an electrical insulating layer directly supports and electrically contacts antiferromagnetic layer 22, and an aluminum cap, 25, is directly supported on chrome platinum antiferromagnetic layer 23. A lower electrical interconnection, 26, a column interconnection conductor, is in electrical contact with plug 24, and a further electrical interconnection, 27, a row interconnection conductor, is in electrical contact with cap 25. The cell array portion shown in FIG. 2 shows a few of row interconnection conductors 27 and column interconnection conductors 26 as they interconnect cells 10 therebetween.
Consider a current being passed through the barrier junction such that the electrons pass from top to bottom in FIG. 1. Polarized electrons tunneling from the upper pinned polarization layer 17 through adjacent barrier layer 15 and into storage ferromagnetic layer 11 will create a torque on the magnetization of layer 11. If the current density and polarization are large enough, the magnetization will rotate to be in the same direction as the magnetization of upper polarization layer 17. As the electrons flow on through inner ruthenium layer 13 to ferromagnetic layer 12, the spins of those electrons are randomized. The tight antiferromagnetic exchange coupling of the two ferromagnetic layers will ensure that the other inner magnetization layer 12 will have its magnetization direction remain antiparallel to the direction of magnetization of layer 11 to form a first magnetic state. Reversing the current will reverse the storage of data on inner magnetic layers 11 and 12 by reversing the orientations of the magnetizations of those two layers to form an alternative second magnetic state.
Retrieving stored information is accomplished by injecting smaller currents (less in magnitude than the current threshold needed for ferromagnetic layer magnetization switching) into each of the outside contacts, and taking both currents out through the storage layers. Observing the voltage difference between the outside electrodes with respect to the inner electrode, which is essentially the voltage drop across the barrier junction, will provide the output signal to indicate the storage state as the barrier junction will be in either its higher magnetoresistance magnetic state or its other in its lower magnetoresistance magnetic state. A logic “one” assigned to one of these magnetic states and a logic “zero” assigned to the other magnetic state will provide corresponding output signals which are of opposite algebraic signs.
A small shape anisotropy for the cell of 40 Oe would require that the current density for switching to be 106 A/cm2. This would require 1.0 mA into a junction of 0.1 square micron area (10-9 cm2). At 100 mV across each junction, the resistance of the junction would have to be 100 Ohm, which is equivalent to 1.0 Ohm-micron2 contact resistance.
Thus, this memory cell can have the magnetization directions of the data storage layers 11 and 12 switched by a fairly low spin injected current of 1 mA, and the output signal, using 0.1 mA to read, would be about 8 mV across the cell for a 40% magnetoresistance. The cell would have a relatively small surface area parallel to the adjacent substrate surface.
However, the need for switching transistors to control the supply of spin polarized electrical currents through the magnetoresistive devices in these cells, as is needed to switch the cells between their alternative magnetic states so as to operate them as memory cells, and also to control the provision of magnetic state sensing currents therethrough, again consumes chip surface area in the integrated circuit chips in which they are provided to result in increasing the costs thereof. A memory cell array biasing technique, however, has been found that allows determining the magnetic state of a spin current switched magnetoresistive device memory cell in the array through establishing a sensing electrical current through that cell, and also electrically biasing other cells, all without needing a switching transistor in the cell to control the sensing current to accomplish this result.
The method proceeds by providing an electrical current for sensing the current cell magnetic state through the magnetoresistive device in a selected cell in the array of cells that goes to ground through that one of the column interconnection conductors of the array to which the selected cell in the array is connected as a result of a part of a switching process used for selecting cells that are to have their magnetic states sensed. This part of the cell selecting process is accomplished through selecting to switch that column interconnection conductor connected to the selected cell to the ground voltage potential by a switch external to the array. This sensing current is supplied from a voltage source external to the array through that one of the row interconnection conductors of the array to which the selected cell is also connected as another part of the switching process used for selecting a cell to have its magnetic state sensed. This part of the process is accomplished through selecting to switch that row connected to the selected cell to a row selection voltage potential of a magnitude, generally, equal approximately to the desired sensing current multiplied by the average resistance value of the array cell magnetoresistive devices.
The remaining row interconnection conductors of the array, other than the one switched to the row selection voltage as described above, are left open with respect to external circuit portions in being unconnected to any voltage potential source. The remaining column interconnection conductors, other than the one switched to ground as described above, are switched to voltage potentials with magnitudes equal to that of the row selection voltage potential which results in all the current established in the row interconnection conductor switched to the row selection voltage passing through the selected cell. Thus, the row selection voltage potential can be chosen to have a magnitude sufficient to provide a detectable voltage difference across the selected cell that results from the different sensing current magnitudes that are established through the magnetoresistive device in the cell in the two alternative magnetic states to which this cell device can be set (through switching sufficient spin currents into it exceeding the cell switching threshold) because of the cell resistance difference between these two states.
Further, the resulting, though unwanted, alternative path currents that are also established through other cells in the array in unavoidably having such currents accompany the provision of such a sensing current with magnitudes equal to a fraction of the magnitude of the sensing current in those cells connected to no more than of either a selected row or column interconnection. These magnitude differences assure that the magnetic states of the magnetoresistive devices in the other cells remain unchanged during the retrieving of the current magnetic state of the magnetoresistive device in that selected memory cell if the selected value of the sensing current is chosen small enough to avoid such a state change in the magnetoresistive device of the selected cell in being sufficiently less than the switching threshold current value.
An approximate demonstration of the electrical currents occurring in the various cells, during the foregoing selected cell magnetic state retrieval biasing process, can be provided for such interconnected cells provided in a voltage biased cross-point cell array in which the memory cells are interconnected to row and column interconnection conductors as described above. The demonstration is based on assuming the magnetoresistive devices in the cells each have a resistance that varies relatively little from the devices average resistance R, and that the resistances of the row interconnection conductors that are connected to the common sides of the corresponding rows of cell devices and of the column interconnection conductors connected to the common opposite sides of corresponding columns of cell devices are all negligible.
In an array of spin current switched magnetoresistive device memory cells having m rows and n columns, the electrical current Iij in each device during steady state conditions in this selected cell magnetic state retrieval biasing process can be represented as the voltage drop across the resistance R of that cell equal to the difference between the voltage Vri of the row interconnection conductor to which it is connected and the voltage Vcj of the column interconnection conductor to which it is connected with 1<i<m and 1<j<n. This can be expressed as a matrix array of such currents and voltages of
                              (                                                                      I                  11                                                                              I                  12                                                            …                                                              I                                      1                    ⁢                    n                                                                                                                        I                  21                                                                              I                  21                                                            …                                                              I                                      2                    ⁢                    n                                                                                                      …                                            …                                                                                                                          …                                                                                      I                                      m                    ⁢                                                                                  ⁢                    1                                                                                                I                                      m                    ⁢                                                                                  ⁢                    1                                                                              …                                                              I                  mn                                                              )                =                              1            R                    ⁢                      {                                          (                                                                                                    V                                                  r                          ⁢                                                                                                          ⁢                          1                                                                                                                                    V                                                  r                          ⁢                                                                                                          ⁢                          1                                                                                                            …                                                                                      V                                                  r                          ⁢                                                                                                          ⁢                          1                                                                                                                                                                        V                                                  r                          ⁢                                                                                                          ⁢                          2                                                                                                                                    V                                                  r                          ⁢                                                                                                          ⁢                          2                                                                                                            …                                                                                      V                                                  r                          ⁢                                                                                                          ⁢                          2                                                                                                                                                …                                                              …                                                                                                                                                                          …                                                                                                                          V                        rm                                                                                                            V                        rm                                                                                    …                                                                                      V                        rm                                                                                            )                            -                              (                                                                                                    V                                                  c                          ⁢                                                                                                          ⁢                          1                                                                                                                                    V                                                  c                          ⁢                                                                                                          ⁢                          2                                                                                                            …                                                                                      V                        cn                                                                                                                                                V                                                  c                          ⁢                                                                                                          ⁢                          1                                                                                                                                    V                                                  c                          ⁢                                                                                                          ⁢                          2                                                                                                            …                                                                                      V                        cn                                                                                                                        …                                                              …                                                                                                                                                                          …                                                                                                                          V                                                  c                          ⁢                                                                                                          ⁢                          1                                                                                                                                    V                                                  c                          ⁢                                                                                                          ⁢                          2                                                                                                            …                                                                                      V                        cn                                                                                            )                                      }                                              (        1        )            
As indicated above, selecting a cell from which to retrieve the current magnetic state thereof through passing a sensing current therethrough involves at a minimum setting its row interconnection conductor to an externally supplied row selection voltage potential of value V (as a representative value, for example) and the column interconnection conductor thereof to ground potential. If this row interconnection conductor is so selected by applying such a row selection voltage thereto, and the corresponding column interconnection is so selected by connecting it to ground potential, then by symmetry, the unselected columns must all have the same voltage, Vc, and the unselected rows must all have the same voltage Vr. This must be true because all unselected rows are identical to each other, and all unselected columns are identical to each other. The electrical currents in the row to which the row selection voltage V is applied will carry the resulting sensing current Is and n−1 half selected currents I1/2r, and the electrical currents received in the column switched to ground potential will be the sense current Is and m−1 half selected currents I1/2c. The devices in the remaining rows and columns will all have by symmetry the same value of unselected current Iu passing through them.
Assume, for example, that the first cell in the first row has been selected by the supplying of the row selection voltage to the first row and the column grounding to the first column to thereby have a resulting sensing current Is, established therein, then the following correspondingly modified matrix arrays result:
                              (                                                                      I                  s                                                                              I                                                            1                      /                      2                                        ⁢                    r                                                                              …                                                              I                                                            1                      /                      2                                        ⁢                    r                                                                                                                        I                                                            1                      /                      2                                        ⁢                    c                                                                                                I                  u                                                            …                                                              I                  u                                                                                    …                                            …                                                                                                                          …                                                                                      I                                                            1                      /                      2                                        ⁢                    c                                                                                                I                  u                                                            …                                                              I                  u                                                              )                =                              1            R                    ⁢                      {                                          (                                                                            V                                                              V                                                              …                                                              V                                                                                                                          V                        r                                                                                                            V                        r                                                                                    …                                                                                      V                        r                                                                                                                        …                                                              …                                                                                                                                                                          …                                                                                                                          V                        r                                                                                                            V                        r                                                                                    …                                                                                      V                        r                                                                                            )                            -                              (                                                                            0                                                                                      V                        c                                                                                    …                                                                                      V                        c                                                                                                                        0                                                                                      V                        c                                                                                    …                                                                                      V                        c                                                                                                                        …                                                              …                                                                                                                                                                          …                                                                                                  0                                                                                      V                        c                                                                                    …                                                                                      V                        c                                                                                            )                                      }                                              (        2        )            
The corresponding array magnetoresistive device currents from this last matrix array can then be seen to beSelected: Is=V/R  (3a)Half-selected Row: I1/2r=(V−Vc)/R  (3b)Half-selected Column: I1/2c=Vr/R  (3c)Unselected: Iu=(Vr−Vc)/R  (3d)
If the row and column interconnections are left without any external bias voltages applied to them, the common voltages of unselected columns Vc and the voltages of the unselected rows Vr can be found through equating the currents in an unselected row interconnection and equating the currents in an unselected column interconnection in accord in each instance with Kirchoff's current conservation law (current into a conductor is equal to current exiting a conductor). That is, sum the currents in an unselected row interconnection conductor of magnetoresistive devices of which one will be connected to a selected column interconnection set to a zero voltage value, or
                                                        V              r                        R                    +                                                    (                                  N                  -                  1                                )                            ·                              (                                                      V                    r                                    -                                      V                    c                                                  )                                      R                          =        0                            (        4        )            and sum the currents in an unselected column interconnection conductor of which one will be connected to a selected row interconnection that is set to the row selection voltage value V, or
                                                        V              -                              V                c                                      R                    +                                                    (                                  M                  -                  1                                )                            ·                              (                                                      V                    r                                    -                                      V                    c                                                  )                                      R                          =        0                            (        5        )            Solving these equations for Vr and Vc yields
                              Selected          ⁢                      :                          ⁢                                  ⁢                              I            s                    =                      V            /            R                                              (                  6          ⁢          a                )                                          Half          ⁢                      -                    ⁢          selected          ⁢                                          ⁢          Row          ⁢                      :                          ⁢                                  ⁢                              I                                          1                /                2                            ⁢              r                                =                                    (                                                m                  -                  1                                                  n                  +                  m                  -                  1                                            )                        ⁢                          V              R                                                          (                  6          ⁢          b                )                                          Half          ⁢                      -                    ⁢          selected          ⁢                                          ⁢          Column          ⁢                      :                          ⁢                                  ⁢                              I                                          1                /                2                            ⁢              c                                =                                    (                                                n                  -                  1                                                  n                  +                  m                  -                  1                                            )                        ⁢                          V              R                                                          (                  6          ⁢          c                )                                          Unselected          ⁢                      :                          ⁢                                  ⁢                              I            u                    =                                    (                                                -                  1                                                  n                  +                  m                  -                  1                                            )                        ⁢                          V              R                                                          (                  6          ⁢          d                )            The equivalent resistance of the array is useful for determining the total current flowing into the array from the row selection voltage source as Itot-in=V/Req, that is, Req equals the row selection voltage value V divided by the input current into the row interconnection conductor selected in the cell selection process, i.e. V divided by the sensing current Is and the other n−1 half selected currents I1/2r in that row to give
                              R          eq                =                              (                                          n                +                m                -                1                                            n                ⁢                                                                  ⁢                m                                      )                    ⁢          R                                    (        7        )            as the array total equivalent resistance.
In the array voltage biasing arrangement described above for determining the magnetic state of a selected cell in the array thereof, the row interconnection conductor connected to the selected cell is switched to a row selection voltage potential and the remaining row interconnection conductors of the array are left open with respect to external circuit portions in being unconnected to any voltage potential source. Also, the column interconnection conductor connected to the selected cell is switched to ground and the remaining column interconnection conductors are switched to voltage potentials with magnitudes equal to that of the row selection voltage potential. This arrangement is indicated in the circuit schematic representation thereof shown in FIG. 3 for an example memory cell array having m rows of cells with the cells in each row each connected at the terminals on one side thereof to a common row interconnection conductor and connected at the terminals on the other side thereof to a corresponding one of n column interconnection conductors. Each cell has a two terminal spin current switched magnetoresistive device element therein represented as having an average electrical circuit resistance value between those terminals of R.
Since there is no voltage drop across the other cells connected to the same row interconnection conductor as is the selected cell since the row and the columns for the other cells are all connected to voltage sources of potential V, only the selected cell connected between that the row interconnection conductor (and to which row selection voltage potential V is connected) and a grounded column interconnection conductor has an electrical current through it. This situation forces that current in the selected cell to equal the row selection voltage potential V less the ground potential of zero divided by the resistance of selected cell, and so will equal the current supplied from the source of the row selection voltage. Hence, the actual resistance corresponding to the magnetic state that the selected cell is in will set the current supplied by the source of the row selection voltage, and so detecting the magnitude of that current at the source of the row selection voltage will reveal the present resistance of, and so the present magnetic state of, the selected cell.
Again, the unselected rows voltages Vr can be found through equating the currents in an unselected row interconnection conductor in accord with Kirchoff's current conservation law. That is, sum the currents in the cell magnetoresistive devices connected to an unselected row interconnection conductor of which one will be connected to a selected column interconnection conductor set to a zero voltage value, and with the rest connected to voltage sources providing a voltage potential V, or
                                                        V              r                        R                    +                                                    (                                  N                  -                  1                                )                            ·                              (                                                      V                    r                                    -                  V                                )                                      R                          =        0                            (        8        )            Solving this equation for Vr and using the column biasing potentials gives
                              Selected          ⁢                      :                          ⁢                                  ⁢                              I            s                    =                      V            /            R                                              (                  9          ⁢          a                )                                          Half          ⁢                      -                    ⁢          selected          ⁢                                          ⁢          Column          ⁢                      :                          ⁢                                  ⁢                              I                                          1                /                2                            ⁢              c                                =                                    (                                                n                  -                  1                                n                            )                        ⁢                          V              R                                                          (                  9          ⁢          b                )                                          Unselected          ⁢                      :                          ⁢                                  ⁢                              I                                          1                /                2                            ⁢              r                                =                                    (                                                -                  1                                n                            )                        ⁢                          V              R                                                          (                  9          ⁢          c                )            
These results are in accord with the foregoing description for sensing magnetic states of selected cells in an array of spin current switched magnetoresistive device memory cells, and so the magnetic states of such memory cells can be determined accurately and without changing the magnetic states of unselected cells all without a transistor switch being provided for each cell in the array. However, such a transistor switch for each cell cannot be eliminated unless also selected magnetic states can established in selected cells without needing such cell transistor switches. Thus, there is a desire for an arrangement that also allows establishing magnetic states in selected ones of such cells without needing such individual cell switches.